RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool

DEVS (Discrete Event System Specification) is widely used in modeling and simulation fields to design, validate, implement complex response systems. provides a robust formalism for system design using event-driven, state-based models with explicitly defined temporal information. We extend the RTL-DEVS model based on enable part of Verilog DEVS-based tools. The methodology, which imitates Verilog’s testbench behavioral module, confirmed through experiments that RTL can be performed sufficiently code elaboration process. In multiple results, RTL-DEVS-based were able output equivalent results under limited conditions. formalism-based extended other simulators when model-type exchange tools, this means advanced functions or classes tools applied higher-level language